The present invention relates to a semiconductor integrated circuit device which matches the trend toward further miniaturization and to a method for designing the same.
If a plurality of functional blocks are formed in one chip, it has not been performed conventionally to provide MOS transistors contained in a plurality of digital functional circuit blocks with different gate lengths or provide the respective gate oxide films of the MOS transistors with different thicknesses.
In an analog circuit or a circuit for which consideration should be given to a latch-up or a breakdown voltage caused by an electrostatic damage (ESD), it has been conventional practice to use different design rules for a transistor provided on the I/O pad portion of the circuit and for the logic portion of the circuit. This is because different power supply voltages are applied thereto.
On the other hand, it has not been performed to use different design rules for process design within one digital functional block or one analog functional block.
It has not been performed, either, to form chips from one wafer by using different masks, form chips with different sizes or different functions from one wafer, or fabricate various chips designed to have different performances from one wafer.
As design sizes are reduced increasingly year after year, however, a chip designing process performed by using one layout design rule for one chip encounters the following problems.
The layout design rule which is 0.13 xcexcm in the year 2001 is expected to become 0.10 xcexcm in the year 2005. If design is to be performed in accordance with the layout design rule of 0.10 xcexcm, a fabrication process requires a patterning accuracy on the order of several tens of nanometers.
In that case, it will become extremely difficult to control variations in patterning accuracy dependent on the regions (portions) of the principal surface of a wafer, i.e., an amount of process variation to several tens of nanometers by considering each of variations in patterning accuracy in the fabrication process, the relationship between the regions (portions) of one chip and layout densities therein, and the like.
If a design rule also considering variations in patterning accuracy is used, a design margin is reduced dramatically so that the yield rate is reduced significantly. As a consequence, the trend toward further miniaturization drastically increases the manufacturing cost for a chip.
In view of the foregoing problems expected, an object of the present invention is to positively match the trend toward a further reduction in design size.
To attain the object, a first method for fabricating a semiconductor integrated circuit device comprises: a first step of forming an insulating film on a semiconductor wafer; and a second step of forming a mask pattern containing a functional element or a wire on the insulating film and patterning the insulating film by using the formed mask pattern, the second step including changing dimensions of the mask pattern in accordance with an amount of process variation caused in a thickness or dielectric constant of the insulating film by at least the first step.
In accordance with the first method for fabricating a semiconductor integrated circuit device, even if a variation occurs in the thickness or dielectric constant of a formed insulating film, a functional element or a wire having a desired electric characteristic can be formed. This substantially reduces an amount of process variation within the semiconductor wafer and thereby allows the miniaturization of elements and the like.
In the first method for fabricating a semiconductor integrated circuit device, the insulating film is preferably a gate insulating film for a transistor.
In the first method for fabricating a semiconductor integrated circuit device, the insulating film is preferably an interlayer insulating film provided between different wiring layers.
Preferably, the first method for fabricating a semiconductor integrated circuit device further comprises the step of partitioning the semiconductor wafer into a plurality of chip formation regions, wherein the second step includes individually measuring the thickness or dielectric constant of the insulating film in each of the chip formation regions.
In the first method for fabricating a semiconductor integrated circuit device, the mask pattern is preferably a gate pattern for forming a transistor and the second step preferably includes changing a gate length dimension of the gate pattern.
In the first method for fabricating a semiconductor integrated circuit device, the mask pattern is preferably a wiring pattern having a plurality of delay circuits connected to each other and the second step preferably includes changing the wiring pattern.
In the first method for fabricating a semiconductor integrated circuit device, the second step preferably includes forming a monitor pattern for allowing the thickness or dielectric constant of the insulating film to be monitored.
A second method for fabricating a semiconductor integrated circuit device comprises: a first step of preparing a plurality of lots each containing a specified number of semiconductor wafers; a second step of forming insulating films on the respective semiconductor wafers; and a third step of forming a mask pattern containing a functional element or a wire on each of the insulating films on the semiconductor wafers and individually patterning each of the insulating films by using the formed mask pattern, the third step including changing dimensions of the mask pattern on a per lot basis in accordance with an amount of process variation caused in a thickness or dielectric constant of the insulating film by the second step.
The second method for fabricating a semiconductor integrated circuit device not only achieves the same effects as the first method for fabricating a semiconductor integrated circuit device of the present invention but also reduces an amount of process variation within the semiconductor wafer on a per lot basis.
In the second method for fabricating a semiconductor integrated circuit device, the third step preferably includes individually measuring the thickness or dielectric constant of the insulating film on each of the semiconductor wafers.
The second method for fabricating a semiconductor integrated circuit device further comprises the step of: partitioning each of the semiconductor wafers into a plurality of chip formation regions, wherein the third step includes individually measuring the thickness or dielectric constant of the insulating film on each of the chip formation regions of the semiconductor wafer.
A third method for fabricating a semiconductor integrated circuit device, the method comprises: a first step of forming insulating films on respective surfaces of a base having a polyhedral configuration; and a second step of forming a mask pattern containing a functional element or a wire on each of the insulating films and patterning the insulating film by using the formed mask pattern, the second step including individually measuring a thickness or dielectric constant of each of the insulating films on the surfaces of the base and changing dimensions of the mask pattern on each of the surfaces.
The third method for fabricating a semiconductor integrated circuit device is not limited to a plate-like semiconductor substrate used commonly. Even if a polyhedral base is used, it achieves the same effects as achieved by the first method for fabricating a semiconductor integrated circuit device of the present invention.
A fourth method for fabricating a semiconductor integrated circuit device comprises: a first step of forming, on a semiconductor wafer, chip formation regions of different sizes; and a second step of forming a functional element in each of the chip formation regions.
Even if the thickness of a film formed on a wafer undergoes fluctuation resulting from process variations, the fourth method for fabricating a semiconductor integrated circuit device substantially reduces an amount of variation since it forms the chip formation regions of different sizes on the semiconductor wafer by defining a chip formation region occupying a relative large area in the region of the semiconductor wafer where fluctuation is small and defining a chip formation region occupying a relative small area in the region of the semiconductor wafer where fluctuation is large. This allows miniaturization of elements and the like.
A fifth method for fabricating a semiconductor integrated circuit device comprises: a first step of forming a film-like member composing a functional element or a wire on a semiconductor wafer having a plurality of chip formation regions; and a second step of patterning the film-like member by using a mask pattern having a specified configuration, the mask pattern having dimensions different from one chip formation region to another in the second step.
In accordance with the fifth method for fabricating a semiconductor integrated circuit device, the dimensions of the mask pattern are different from one chip formation region to another in the second step. This substantially reduces an amount of process variation occurring in the first step during the patterning of the film-like member so that elements and the like are miniaturized.